Semiconductor device with SI-GE layer-containing low resistance, tunable contact

ABSTRACT

The present invention provides a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si x Ge 1−x  (0&lt;x&lt;1) layer. Thus, only moderate doping is required, which in turn protects the device from short channel effect and leakage. The low resistance, tunable contact is suitable for CMOS devices.

[0001] This application is a divisional of co-pending application Ser. No. 10/035,221, filed on Jan. 4, 2002, the entire contents of which are hereby incorporated by reference and for which priority is claimed under 35 U.S.C. § 120.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention:

[0003] The present invention relates to a semiconductor device with a metal/semiconductor interface, and more particularly to a semiconductor device in which a low resistance, tunable contact is formed by means of using a Si_(x)Ge_(1−x) (0<x<1) layer.

[0004] 2. Description of the Prior Art:

[0005] It has been customary in modern semiconductor manufacturing technique to form MS (metal-semiconductor) contact by forming is either an Ohmic contact or a diffusion contact. The former technique is performed by implanting dopants into the MS interface layer to a concentration above solid solubility limit (i.e. N(n,p)>10²⁰ cm⁻³) to form a tunneling barrier. On the other hand, the latter technique is performed by diffusing dopants into the interface layer to lower the Schottky Barrier Height (SBH).

[0006] Silicon, a frequently used semiconductor, has a high intrinsic SBH (or Eg (energy gap)), Eg=1.11 eV. Therefore, when silicon is used, a relatively high doping concentration is required at the MS interface layer, which is usually performed using high-energy implantation, to lower the SBH in order to form a better contact. However, the high-energy implantation results in unwanted deep contact junctions, which subjects the device to short channel effect (SCE) or punch-through (leakage).

SUMMARY OF THE INVENTION

[0007] An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device having a metal/semiconductor interface with low resistance contact.

[0008] Another object of the present invention is to provide a process to form a low resistance contact at a metal/semiconductor interface using moderate doping requirements, which in turn protect the device from short channel effect and leakage.

[0009] A further object of the present invention is to provide a low resistance, tunable contact suitable for CMOS devices.

[0010] To achieve the above objects, the semiconductor device of the present invention includes a semiconductor substrate; a dielectric layer on the semiconductor substrate, having a contact opening exposing the semiconductor substrate; a Si_(x)Ge_(1−x)-layer formed within the contact opening, wherein 0<x<1; and a metal plug over the Si_(x)Ge_(1−x) layer filling the contact opening.

[0011] The present invention also provides a process to form a metal contact at a metal/semiconductor interface. First, a dielectric layer is formed on a semiconductor substrate. A contact opening is formed in the dielectric layer to expose the semiconductor substrate. A Si_(x)Ge_(1−x) layer is formed in the contact opening, wherein 0<x<1. Finally, a metal plug is filled over the Si_(x)Ge_(1−x) layer into the contact opening.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.

[0013]FIGS. 1a to 1 e are cross-sections illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a first embodiment of the present invention.

[0014]FIGS. 2a to 2 d are cross-sections illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a second embodiment of the present invention, wherein a consumable polysilicon layer is selectively formed on the Si—Ge layer.

[0015]FIGS. 3a to 3 e are cross-sections illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a third embodiment of the present invention, wherein a conformal consumable polysilicon is formed.

[0016]FIGS. 4a to 4 e are cross-sections illustrate the process flow of fabricating a CMOS according to a fourth embodiment of the present invention.

[0017]FIG. 5 is a cross-section of a CMOS according to a fifth embodiment of the present invention.

[0018]FIG. 6 is a cross-section of a CMOS according to a sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The band gap energy of Si_(x)Ge_(1−x) varies from 0.67 eV (x=0) to 1.11 eV (x=1). That is to say, Si_(x)Ge_(1−x) (0<x<1) has a lower band gap energy than pure silicon.

[0020] The main feature of the present invention resides in that a Si_(x)Ge_(1−x) layer (0<x<1), a lower band gap energy semiconductor material, is formed within a contact opening at a metal/semiconductor interface. Lower band gap energy will reduce the SBH of metal-semiconductor (MS) interface by lowering the Fermi level of the MS. The lowered SBH will lower the contact resistance, thus, a good contact at the metal/semiconductor interface can be formed using moderate doping requirements. This in turn protects the device from short channel effect and leakage.

[0021] First, FIGS. 1a to 1 e illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a first embodiment of the present invention.

[0022] In FIG. 1a, a dielectric layer 20 is formed on a semiconductor substrate 10. A contact opening 30 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Next, a Si_(x)Ge_(1−x) layer 40 (0<x<1) is formed in the contact opening 30.

[0023] The Si_(x)Ge_(1−x) 40 can be formed by a variety of methods, such as MBE (molecular beam epitaxy), UHV-CVD (ultra-high vacuum chemical vapor deposition), RT-CVD (rapid thermal CVD), and LRP-CVD (limited reaction processing CVD). For example, the Si_(x)Ge_(1−x) layer 40 can be formed by selective epitaxial growth at a relatively low temperature range (<800° C.).

[0024] The Si_(x)Ge_(1−x) layer 40 is preferably a silicon-rich Si_(x)Ge_(1−x) layer, which has properties closer to those of pure silicon. This causes a less chance of dislocation. For example, x is preferably in the range of 0.5<x<0.95.

[0025] It has been reported that a thin layer of SiGe thinner than a critical thickness, which varies depending upon its stochiometry and deposition conditions, does not cause a dislocation in silicon substrate even with high temperature post processes. Therefore, it shall be noted that the Si_(x)Ge_(1−x) layer 40 thickness should be controlled to be less than the critical thickness to maintain it as a strained state not to cause dislocation in silicon substrate due to its lattice mismatch between silicon and SiGe, otherwise the junction will be leaky.

[0026] The Si_(x)Ge_(1−x) layer 40 is preferably a strained Si_(x)Ge_(1−x) layer not causing dislocation in the semiconductor substrate 10. The Si_(x)Ge_(1−x) layer 40 is preferably more than or equal to 5 nm and less than or equal to 30 nm. Thus, a low resistance Ohmic contact can be achieved.

[0027] Subsequently, in FIG. 1b, a metal layer 50 is formed on the Si_(x)Ge_(1−x) layer 40. For example, the metal layer can be composed of a glue layer 52 and a diffusion barrier layer 54, which are formed both on the Si_(x)Ge_(1−x) layer 40 and on the sides of the contact opening 30. The glue layer 52 can be a titanium (Ti) layer, which has good adhesion to dielectric layer 20. The diffusion barrier layer 54 can be a TiN layer, serving as a diffusion barrier to protect the semiconductor silicon substrate 10 from fluorine attack during post tungsten deposition processes. Alternatively, the glue/diffusion barrier layer can also be a W/WN layer.

[0028] Subsequently, in FIG. 1c, a dopant is implanted into the metal layer 50 and the Si_(x)Ge_(1−x) layer 40. The implanting can be conducted at a low energy (100 eV to 10 KeV) and low dose(1E14 atoms/cm² to 1E5 atoms/cm²), or preferably conducted at a high energy (20 KeV to 80 KeV) and low dose (5E14 atoms/cm² to 3E15 atoms/cm²). Alternatively, the implanting can be conducted by an ion mixing method. That is, first, a low energy (100 eV to 10 KeV) and high dose (1×10¹⁵ to 1×10¹⁶ atoms/cm²) implantation is conducted, then, a high energy (20 KeV to 80 KeV) and low dose (5E13 to 5E14 atoms/cm²) is conducted. The low energy, high dose implanation can be performed by PLAD (plasma doping) or alternatively PIII (plasma ion immersion implantation). The high energy, low dose implantation can be performed by conventional beam-line I/I (ion implantation).

[0029] Subsequently, in FIG. 1d, annealing is conducted to transform the metal layer 50 into a metal silicide layer 90 and to diffuse the dopant into the semiconductor substrate 10 in a SADS (salicide as a doping source) manner to form a diffusion region 60. It can be seen in the figure that a portion of the Si_(x)Ge_(1−x) layer 40 is consumed to form the metal silicide layer 90. Thus, the Si_(x)Ge_(1−x) layer 40 becomes thinner, which adversely affects the SBH of the Si_(x)Ge_(1−x) layer 40. Therefore, a thicker Si_(x)Ge_(1−x) layer 40, for example, more than 30 nm, can be formed to compensate the consumed portion during the silicidation process. Thus, an adequately thick Si_(x)Ge_(1−x) layer 40 can still be retained to maintain low SBH.

[0030] Finally, in FIG. 1e, a metal plug 70 is filled on the metal layer 50 into the contact opening 30. For example, a tungsten layer is formed by selective tungsten deposition. Then, chemical mechanical polishing (CMP) is performed to planarize the tungsten layer and remove the metal layer 50 on the dielectric layer 20.

[0031] Now FIGS. 2a to 2 d illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a second embodiment of the present invention. Unlike the first embodiment, this embodiment selectively forms a consumable polysilicon layer on the Si—Ge layer. The numerals are the same as in FIGS. 1a to 1 e in order to represent the same elements.

[0032] In FIG. 2a, a dielectric layer 20 is formed on a semiconductor substrate 10. A contact opening 30 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Next, a Si_(x)Ge_(1−x) layer 40 (0<x<1) is formed in the contact opening 30. Next, a consumable polysilicon layer 80 is formed only on the Si_(x)Ge_(1−x) layer 40.

[0033] Subsequently, in FIG. 2b, a metal layer 50 is formed on the consumable polysilicon layer 80. For example, the metal layer can be composed of a glue layer 52 and a diffusion barrier layer 54, which are formed both on polysilicon layer 80 and on the sides of the contact opening 30. The glue layer 52 can be a titanium (Ti) layer and the diffusion barrier layer 54 can be a TiN layer. Next, a dopant is implanted into the metal layer 50, the polysilicon layer 80, and the Si_(x)Ge_(1−x) layer 40. The implanting condition can be the same as described in the first embodiment.

[0034] Subsequently, in FIG. 2c, annealing is conducted to transform the metal layer 50 into a metal silicide layer 92 and to diffuse the dopant into the semiconductor substrate 10 in a SADS (salicide as a doping source) manner to form a diffusion region 60. It can be seen in the figure that a portion of consumable polysilicon layer 80 is consumed to form the metal silicide layer 92. Thus, in the silicidation step, the polysilicon layer 80 instead of the Si_(x)Ge_(1−x) layer is consumed. This can maintain the integrity of the Si_(x)Ge_(1−x) layer 40 without becoming thinner, thereby the low SBH can be maintained. In order to allow the polysilicon layer 80 consumed in the silicidation step, while not consuming the Si_(x)Ge_(1−x) layer 40, the polysilicon layer 80 should be adequately thick, preferably with a thickness of 10 nm to 50 nm.

[0035] Finally, in FIG. 2d, a metal plug 70 is filled on the metal layer 50 into the contact opening 30. For example, a tungsten layer is formed by selective tungsten deposition. Then, chemical mechanical polishing (CMP) is performed to planarize the tungsten layer and remove the metal layer 50 on the dielectric layer 20.

[0036]FIGS. 3a to 3 e illustrate the process flow of fabricating a metal contact at a metal/semiconductor interface according to a third embodiment of the present invention. Unlike the first embodiment, this embodiment forms a conformal consumable polysilicon on the Si_(x)Ge_(1−x) layer. The numerals are the same as in FIGS. 1a to 1 e in order to represent the same elements.

[0037] In FIG. 3a, a dielectric layer 20 is formed on a semiconductor substrate 10. A contact opening 30 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Next, a Si_(x)Ge_(1−x) layer 40 (0<x<1) is formed in the contact opening 30. Next, a consumable polysilicon layer 82 is conformally formed both on the Si_(x)Ge_(1−x) layer 40 and on the sides of the contact opening 30.

[0038] Subsequently, in FIG. 3b, a metal layer 50 is formed on the consumable polysilicon layer 82. For example, the metal layer can be a diffusion barrier layer such as TiN layer.

[0039] Subsequently, in FIG. 3c, a dopant is implanted into the metal layer 50, the polysilicon layer 82, and the Si_(x)Ge_(1−x) layer 40. The implanting condition can be the same as described in the first embodiment.

[0040] Subsequently, in FIG. 3d, annealing is conducted to transform the metal layer 50 into a metal silicide layer 94 and to diffuse the dopant into the semiconductor substrate 10 in a SADS (salicide as a doping source) manner to form a diffusion region 60. It can be seen in the figure that a portion of the consumable polysilicon layer 82 is consumed to form the metal silicide layer 94. Thus, in the silicidation step, the polysilicon layer 82 instead of the Si_(x)Ge_(1−x) layer 40 is consumed. This can maintain the integrity of the Si_(x)Ge_(1−x) layer 40 without it becoming thinner, thereby the low SBH can be maintained. In order to allow the polysilicon layer 82 to be consumed in the silicidation step, while not consuming the Si_(x)Ge_(1−x) layer 40, the polysilicon layer 82 should be adequately thick, preferably with a thickness of 10 nm to 50 nm.

[0041] Finally, in FIG. 3e, a metal plug 70 is filled on the metal layer 50 into the contact opening 30. For example, a tungsten layer is formed by selective tungsten deposition. Then, chemical mechanical polishing (CMP) is performed to planarize the tungsten layer and remove the metal layer 50 on the dielectric layer 20.

[0042] In this embodiment, the consumable polysilicon layer 82 is conformally formed, that is, it is formed both on the Si_(x)Ge_(1−x) layer 40 and on the sides of the contact opening 30. Since a polysilicon layer serves as an excellent glue layer to the dielectric layer 20, titanium or other glue layers to ILD (inter layer dielectric) may be omitted. This can cut down the production cost.

[0043] The metal contact of the present invention can be readily integrated with a CMOS device. FIGS. 4a to 4 e illustrate the process flow of fabricating a CMOS according to a fourth embodiment of the present invention. In FIG. 4a, separate N-well 120 and P-well 140 are formed in a semiconductor substrate 100 by selectively implanting the appropriate dopant in each well area. Next, shallow trench isolation (STI) is formed to isolate the active device areas wherein the field effect transistor (FET) devices are to be built. Next, a thermal oxide is grown to form a gate oxide 220. Next, a polysilicon layer 240 is formed to constitute a gate structure for the N-channel and P-channel FETs. Next, source/drain areas 610 in the N-well 120 and source/drain areas 620 in the P-well 140 are separately formed.

[0044] Subsequently, a dielectric layer 200 is formed on the substrate 100. A contact opening 300 to the source/drain areas 610 and 620 is formed in the dielectric layer 200 to expose the semiconductor substrate 100. Next, a Si_(x)Ge_(1−x) layer 400 (0<x<1) is formed in the contact opening 300.

[0045] Subsequently, a metal layer 500 is formed on the Si_(x)Ge_(1−x) layer 400. For example, the metal layer can be composed of a glue layer 520 and a diffusion barrier layer 540, which are formed both on the Si_(x)Ge_(1−x) layer 400 and on the sides of the contact opening 300. The glue layer 520 can be a titanium (Ti) layer, which has good adhesion to dielectric layer 200. The diffusion barrier layer 540 can be a TiN layer, serving as a diffusion barrier to protect the semiconductor silicon substrate 100 from fluorine attack during post tungsten deposition processes. Alternatively, the glue/diffusion barrier layer can also be a W/WN layer.

[0046] Subsequently, in FIG. 4b, a photoresist layer 320 is formed to mask the P-well area. The substrate is then subjected to implantation, that is, a P-type dopant such as boron or boron fluoride is implanted into the metal layer 500 and the Si_(x)Ge_(1−x) layer 400 in the N-well area.

[0047] Subsequently, in FIG. 4c, a photoresist layer 340 is formed to mask the N-well area. The substrate is then subjected to implantation, that is, a N-type dopant such as arsenic or phosphorous is implanted into the metal layer 500 and the Si_(x)Ge_(1−x) layer 400 in the P-well area.

[0048] Subsequently, in FIG. 4d, annealing is conducted to transform the metal layer 500 into a metal silicide layer 920 and to diffuse the dopant into the semiconductor substrate 100 in a SADS (salicide as a doping source) manner to form a diffusion region 630 in the source/drain area 610 in the N-well 120 and diffusion region 640 in the source/drain area 620 in the P-well 140.

[0049] Finally, in FIG. 4e, a metal plug 700 is filled on the metal layer 500 into the contact opening 300. For example, a tungsten layer is formed by selective tungsten deposition. Then, chemical mechanical polishing (CMP) is performed to planarize the tungsten layer and remove the metal layer 500 on the dielectric layer 200.

[0050]FIG. 5 shows a cross-section of a CMOS according to a fifth embodiment of the present invention. This CMOS structure is the same as that of the fourth embodiment, except that this embodiment additionally selectively forms a consumable polysilicon layer 800 between the Si_(x)Ge_(1−x) layer 400 and the metal layer 500. The numerals are the same as in FIGS. 4a to 4 e in order to represent the same elements. The procedures for fabricating the CMOS of FIG. 5 are similar to those for fabricating the CMOS of FIG. 4e and are omitted to avoid redundance. Please refer also to FIGS. 2a to 2 d. As described above, a portion of the consumable polysilicon layer 800 is consumed to form the metal silicide layer 940. Thus, in the silicidation step, the polysilicon layer 800 instead of the Si_(x)Ge_(1−x) layer 400 is consumed. This can maintain the integrity of the Si_(x)Ge_(1−x) layer 400 without it becoming thinner, thereby the low SBH can be maintained.

[0051] Now refer to FIG. 6, showing a cross-section of a CMOS according to a sixth embodiment of the present invention. This CMOS structure is the same as that of the fourth embodiment, except that this embodiment additionally forms a conformal consumable polysilicon layer 820 between the Si—Ge layer 400 and the metal layer 500. The numerals are the same as in FIGS. 4a to 4 e in order to represent the same elements. The procedures for fabricating the CMOS of FIG. 5 are similar to those for fabricating the CMOS of FIG. 4e and are omitted to avoid redundance. Please also FIGS. 3a to 3 e. As described above, a portion of the consumable polysilicon layer 820 is consumed to form the metal silicide layer 960. Thus, in the silicidation step, the polysilicon layer 820 instead of the Si_(x)Ge_(1−x) layer 400 is consumed. This can maintain the integrity of the Si_(x)Ge_(1−x) layer 400 without becoming thinner, thereby the low SBH can be maintained. Moreover, in this embodiment, the consumable polysilicon layer 820 is conformally formed, that is, it is formed both on the Si_(x)Ge_(1−x) layer 400 and on the sides of the contact opening 300. Since a polysilicon layer serves as an excellent glue layer to the dielectric layer 200, titanium or other glue layers to ILD may be omitted. This can cut down the production cost.

[0052] The foregoing description of the preferred embodiments of this invention has been presented for purposes of illustration and description. Obvious modifications or variations are possible in light of the above teaching. The embodiments chosen and described provide an excellent illustration of the principles of this invention and its practical application to thereby enable those skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the present invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled. 

What is claimed is:
 1. A semiconductor device comprising: a semiconductor substrate; a dielectric layer on the semiconductor substrate, having a contact opening exposing the semiconductor substrate; a Si_(x)Ge_(1−x) layer formed within the contact opening, wherein 0<x<1; and a metal plug over the Si_(x)Ge_(1−x) layer filling the contact opening.
 2. The semiconductor device as claimed in claim 1, wherein the Si_(x)Ge_(1−x) layer is a silicon-rich Si_(x)Ge_(1−x) layer and 0.5<x<0.95.
 3. The semiconductor device as claimed in claim 1, wherein the Si_(x)Ge_(1−x) layer is a strained Si_(x)Ge_(1−x) layer not causing dislocation in the semiconductor substrate.
 4. The semiconductor device as claimed in claim 1, wherein the Si_(x)Ge_(1−x) layer has a thickness more than or equal to 5 nm and less than or equal to 30 nm.
 5. The semiconductor device as claimed in claim 1, further comprising a metal silicide layer between the Si_(x)Ge_(1−x) layer and the metal plug.
 6. The semiconductor device as claimed in claim 1, further comprising a glue layer and a diffusion barrier layer between the Si_(x)Ge_(1−x) layer and the metal plug, wherein the glue layer and diffusion barrier layer are formed both on the Si_(x)Ge_(1−x) layer and on the sides of the contact opening.
 7. The semiconductor device as claimed in claim 5, wherein the Si_(x)Ge_(1−x) layer has a thickness more than 30 nm.
 8. The semiconductor device as claimed in claim 5, further comprising a diffusion region in the semiconductor substrate under the Si_(x)Ge_(1−x) layer.
 9. The semiconductor device as claimed in claim 1, further comprising a consumable polysilicon layer on the Si_(x)Ge_(1−x) layer.
 10. The semiconductor device as claimed in claim 9, further comprising a metal silicide layer between the polysilicon layer and the metal plug.
 11. The semiconductor device as claimed in claim 10, further comprising a glue layer and a diffusion barrier layer between the consumable polysilicon layer and the metal plug, wherein the glue layer and diffusion barrier layer are formed both on the consumable polysilicon layer and on the sides of the contact opening.
 12. The semiconductor device as claimed in claim 9, wherein the consumable polysilicon layer is formed both on the Si_(x)Ge_(1−x) layer and on the sides of the contact opening.
 13. The semiconductor device as claimed in claim 12, further comprising a metal silicide layer between the polysilicon layer and the metal plug.
 14. The semiconductor device as claimed in claim 13, further comprising a diffusion barrier layer between the consumable polysilicon layer and the metal plug, wherein the diffusion barrier layer are formed both on the consumable polysil icon layer and on the sides of the contact opening.
 15. The semiconductor device as claimed in claim 9, wherein the consumable polysilicon layer has a thickness of 10 nm to 50 nm.
 16. The semiconductor device as claimed in claim 1, wherein the semiconductor device is a CMOS device. 